Philips LPC2101 - Interrupt Register (IR, TIMER0: T0 IR - 0 Xe000 4000 and TIMER1: T1 IR - 0 Xe000 8000); Timer Control Register (TCR, TIMER0: T0 TCR - 0 Xe000 4004 and TIMER1: T1 TCR - 0 Xe000 8004)

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 190
Philips Semiconductors
UM10161
Volume 1 Chapter 15: Timer0 and Timer1
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
15.5.1 Interrupt Register (IR, TIMER0: T0IR - 0xE000 4000 and TIMER1: T1IR
- 0xE000 8000)
The Interrupt Register consists of four bits for the match interrupts and four bits for the
capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be
HIGH. Otherwise, the bit will be LOW. Writing a logic one to the corresponding IR bit will
reset the interrupt. Writing a zero has no effect.
15.5.2 Timer Control Register (TCR, TIMER0: T0TCR - 0xE000 4004 and
TIMER1: T1TCR - 0xE000 8004)
The Timer Control Register (TCR) is used to control the operation of the Timer/Counter.
EMR External Match Register. The EMR controls the
external match pins MAT0.2.0 and MAT1.3.0.
Note: MAT0.3 is not connected to a pin on
LPC2101/02/03.
R/W 0 0xE000 403C
T0EMR
0xE000 803C
T1EMR
CTCR Count Control Register. The CTCR selects between
Timer and Counter mode, and in Counter mode
selects the signal and edge(s) for counting.
R/W 0 0xE000 4070
T0CTCR
0xE000 8070
T1CTCR
PWMCON PWM Control Register. The PWMCON enables
PWM mode for the external match pins MAT0.3.0
and MAT1.3.0.
R/W 0 0xE000 4074
PWM0CON
0xE000 8074
PWM1CON
Table 165: TIMER/COUNTER0 and TIMER/COUNTER1 register map
Generic
Name
Description Access Reset
value
[1]
TIMER/
COUNTER0
Address &
Name
TIMER/
COUNTER1
Address &
Name
Table 166: Interrupt Register (IR, TIMER0: T0IR - address 0xE000 4000 and TIMER1: T1IR - address 0xE000 8000) bit
description
Bit Symbol Description Reset value
0 MR0 Interrupt Interrupt flag for match channel 0. 0
1 MR1 Interrupt Interrupt flag for match channel 1. 0
2 MR2 Interrupt Interrupt flag for match channel 2. 0
3 MR3 Interrupt Interrupt flag for match channel 3. 0
4 CR0 Interrupt Interrupt flag for capture channel 0 event. 0
5 CR1 Interrupt Interrupt flag for capture channel 1 event. 0
6 CR2 Interrupt Interrupt flag for capture channel 2 event. 0
7 CR3 Interrupt Interrupt flag for capture channel 3 event.
Note: CAP0.3 not usable on Timer 0
0