© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 77
Philips Semiconductors
UM10161
Volume 1 Chapter 8: GPIO
Aside from the 32-bit long and word only accessible FIOSET register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed in
Tabl e 7 6
. Next to providing the same functions as the FIOSET register, these additional
registers allow easier and faster access to the physical port pins.
8.4.5 GPIO port 0 output Clear register (IOCLR, Port 0: IO0CLR -
0xE002 800C; FIOCLR, Port 0: FIO0CLR - 0x3FFF C01C)
This register is used to produce a LOW level output at port pins configured as GPIO in an
OUTPUT mode. Writing 1 produces a LOW level at the corresponding port pin and clears
the corresponding bit in the IOSET register. Writing 0 has no effect. If any pin is configured
as an input or a secondary function, writing to IOCLR has no effect.
IO0CLR is the legacy register while the enhanced GPIOs are supported via the FIO0CLR
register. Access to a port pins via the FIOCLR register is conditioned by the
corresponding FIOMASK register (see Section 8.4.2 “
Fast GPIO port 0 Mask register
(FIOMASK, Port 0: FIO0MASK - 0x3FFF C010)”).
Table 74: GPIO port 0 output Set register (IO0SET - address 0xE002 8004 bit description
Bit Symbol Description Reset value
31:0 P0xSET Slow GPIO output value Set bits. Bit 0 in IO0SET corresponds to P0.0 ... Bit 31
in IO0SET corresponds to P0.31.
0x0000 0000
Table 75: Fast GPIO port 0 output Set register (FIO0SET - address 0x3FFF C018) bit description
Bit Symbol Description Reset value
31:0 FP0xSET Fast GPIO output value Set bits. Bit 0 in FIO0SET corresponds to P0.0 ... Bit 31
in FIO0SET corresponds to P0.31.
0x0000 0000
Table 76: Fast GPIO port 0 output Set byte and half-word accessible register description
Register
name
Register
length (bits)
& access
Address Description Reset
value
FIO0SET0 8 (byte) 0x3FFF C018 Fast GPIO Port 0 output Set register 0. Bit 0 in FIO0SET0 register
corresponds to P0.0 ... bit 7 to P0.7.
0x00
FIO0SET1 8 (byte) 0x3FFF C019 Fast GPIO Port 0 output Set register 1. Bit 0 in FIO0SET1 register
corresponds to P0.8 ... bit 7 to P0.15.
0x00
FIO0SET2 8 (byte) 0x3FFF C01A Fast GPIO Port 0 output Set register 2. Bit 0 in FIO0SET2 register
corresponds to P0.16 ... bit 7 to P0.23.
0x00
FIO0SET3 8 (byte) 0x3FFF C01B Fast GPIO Port 0 output Set register 3. Bit 0 in FIO0SET3 register
corresponds to P0.24 ... bit 7 to P0.31.
0x00
FIO0SETL 16
(half-word)
0x3FFF C018 Fast GPIO Port 0 output Set Lower half-word register. Bit 0 in
FIO0SETL register corresponds to P0.0 ... bit 15 to P0.15.
0x0000
FIO0SETU 16
(half-word)
0x3FFF C01A Fast GPIO Port 0 output Set Upper half-word register. Bit 0 in
FIO0SETU register corresponds to P0.16 ... bit 15 to P0.31.
0x0000
Table 77: GPIO port 0 output Clear register 0 (IO0CLR - address 0xE002 800C) bit description
Bit Symbol Description Reset value
31:0 P0xCLR Slow GPIO output value Clear bits. Bit 0 in IO0CLR corresponds to P0.0 ... Bit
31 in IO0CLR corresponds to P0.31.
0x0000 0000
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