© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 27
Philips Semiconductors
UM10161
Volume 1 Chapter 3: System control block
The PLL must be set up, enabled, and Lock established before it may be used as a clock
source. When switching from the oscillator clock to the PLL output or vice versa, internal
circuitry synchronizes the operation in order to ensure that glitches are not generated.
Hardware does not insure that the PLL is locked before it is connected or automatically
disconnect the PLL if lock is lost during operation. In the event of loss of PLL lock, it is
likely that the oscillator clock has become unstable and disconnecting the PLL will not
remedy the situation.
3.8.3 PLL Configuration register (PLLCFG - 0xE01F C084)
The PLLCFG register contains the PLL multiplier and divider values. Changes to the
PLLCFG register do not take effect until a correct PLL feed sequence has been given (see
Section 3.8.7 “
PLL Feed register (PLLFEED - 0xE01F C08C)” on page 29). Calculations
for the PLL frequency, and multiplier and divider values are found in the PLL Frequency
Calculation section on Section 3.8.9 “
PLL frequency calculation” on page 29.
3.8.4 PLL Status register (PLLSTAT - 0xE01F C088)
The read-only PLLSTAT register provides the actual PLL parameters that are in effect at
the time it is read, as well as the PLL status. PLLSTAT may disagree with values found in
PLLCON and PLLCFG because changes to those registers do not take effect until a
proper PLL feed has occurred (see Section 3.8.7 “
PLL Feed register (PLLFEED -
0xE01F C08C)”).
Table 16: PLL Control register (PLLCON - address 0xE01F C080) bit description
Bit Symbol Description Reset
value
0 PLLE PLL Enable. When one, and after a valid PLL feed, this bit will
activate the PLL and allow it to lock to the requested frequency. See
PLLSTAT register, Ta ble 1 8
.
0
1 PLLC PLL Connect. When PLLC and PLLE are both set to one, and after a
valid PLL feed, connects the PLL as the clock source for the
microcontroller. Otherwise, the oscillator clock is used directly by the
microcontroller. See PLLSTAT register, Ta ble 1 8
.
0
7:2 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
Table 17: PLL Configuration register (PLLCFG - address 0xE01F C084) bit description
Bit Symbol Description Reset
value
4:0 MSEL PLL Multiplier value. Supplies the value "M" in the PLL frequency
calculations.
Note: For details on selecting the right value for MSEL see Section
3.8.9 “PLL frequency calculation” on page 29.
0
6:5 PSEL PLL Divider value. Supplies the value "P" in the PLL frequency
calculations.
Note: For details on selecting the right value for PSEL see Section
3.8.9 “PLL frequency calculation” on page 29.
0
7 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
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