© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 107
Philips Semiconductors
UM10161
Volume 1 Chapter 10: UART1
[1] Values "0000" (see Table note 2), “0011”, “0101”, “0111”, “1000”, “1001”, “1010”,
“1011”,”1101”,”1110”,”1111” are reserved.
[2] For details see Section 10.3.11 “
UART1 Line Status Register (U1LSR - 0xE001 0014, Read Only)”
[3] For details see Section 10.3.1 “UART1 Receiver Buffer Register (U1RBR - 0xE001 0000, when DLAB = 0
Read Only)”
[4] For details see Section 10.3.7 “UART1 Interrupt Identification Register (U1IIR - 0xE001 0008, Read Only)”
and Section 10.3.2 “
UART1 Transmitter Holding Register (U1THR - 0xE001 0000, when DLAB = 0 Write
Only)”
The UART1 THRE interrupt (U1IIR[3:1] = 001) is a third level interrupt and is activated
when the UART1 THR FIFO is empty provided certain initialization conditions have been
met. These initialization conditions are intended to give the UART1 THR FIFO a chance to
fill up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the U1THR at one time since
the last THRE = 1 event. This delay is provided to give the CPU time to write data to
U1THR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UART1 THR FIFO has held two or more characters at one time and
currently, the U1THR is empty. The THRE interrupt is reset when a U1THR write occurs or
a read of the U1IIR occurs and the THRE is the highest interrupt (U1IIR[3:1] = 001).
The modem interrupt (U1IIR[3:1] = 000) is available in LPC2104/05/06. It is the lowest
priority interrupt and is activated whenever there is any state change on modem inputs
pins, DCD, DSR or CTS. In addition, a LOW to high transition on modem input RI will
generate a modem interrupt. The source of the modem interrupt can be determined by
examining U1MSR[3:0]. A U1MSR read will clear the modem interrupt.
10.3.8 UART1 FIFO Control Register (U1FCR - 0xE001 0008)
The U1FCR controls the operation of the UART1 RX and TX FIFOs.
Table 107: UART1 interrupt handling
U1IIR[3:0]
value
[1]
Priority Interrupt Type Interrupt Source Interrupt Reset
0001 - None None -
0110 Highest RX Line Status / Error OE
[2]
or PE
[2]
or FE
[2]
or BI
[2]
U1LSR Read
[2]
0100 Second RX Data Available Rx data available or trigger level reached in FIFO
(U1FCR0=1)
U1RBR Read
[3]
or
UART1 FIFO drops
below trigger level
1100 Second Character Time-out
indication
Minimum of one character in the RX FIFO and no
character input or removed during a time period
depending on how many characters are in FIFO
and what the trigger level is set at (3.5 to 4.5
character times).
The exact time will be:
[(word length) × 7
− 2] × 8 + [(trigger level −
number of characters) × 8 + 1] RCLKs
U1RBR Read
[3]
0010 Third THRE THRE
[2]
U1IIR Read
[4]
(if source
of interrupt) or THR write
0000 Fourth Modem Status CTS or DSR or RI or DCD MSR Read
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