Philips LPC2101 - Chapter 3: System Control Block; Pin Description; Summary of System Control Block Functions

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 15
3.1 Summary of system control block functions
The System control block includes several system features and control registers for a
number of functions that are not related to specific peripheral devices. These include:
• Crystal oscillator
• External interrupt inputs
• Miscellaneous system controls and status
• Memory mapping control
• PLL
• Power control
• Reset
• APB divider
• Wake-up timer
Each type of function has its own register(s) if any are required, and unneeded bits are
defined as reserved in order to allow future expansion. Unrelated functions never share
the same register addresses
3.2 Pin description
Tabl e 5 shows pins that are associated with System Control block functions.
UM10161
Chapter 3: System control block
Rev. 01 — 12 January 2006 User manual
Table 5: Pin summary
Pin name Pin
direction
Pin description
X1 Input Crystal Oscillator Input - Input to the oscillator and internal clock
generator circuits
X2 Output Crystal Oscillator Output - Output from the oscillator amplifier
EINT0 Input External Interrupt Input 0 - An active LOW/HIGH level or
falling/rising edge general purpose interrupt input. This pin may be
used to wake up the processor from Idle or Power-down modes.
Pin P0.16 can be selected to perform EINT0 function.
EINT1 Input External Interrupt Input 1 - See the EINT0 description above.
Pin P0.14 can be selected to perform EINT1 function.
Important: LOW level on pin P0.14 immediately after reset is
considered as an external hardware request to start the ISP
command handler. More details on ISP and Serial Boot Loader can
be found in Section 19.4 on page 229
.
EINT2 Input External Interrupt Input 2 - See the EINT0 description above.
Pins P0.7 and P0.15 can be selected to perform EINT2 function.
RESET
Input External Reset input - A LOW on this pin resets the chip, causing
I/O ports and peripherals to take on their default states, and the
processor to begin execution at address 0x0000 0000.