Philips LPC2101 - PLL Control Register (PLLCON - 0 Xe01 F C080)

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 26
Philips Semiconductors
UM10161
Volume 1 Chapter 3: System control block
3.8.2 PLL Control register (PLLCON - 0xE01F C080)
The PLLCON register contains the bits that enable and connect the PLL. Enabling the
PLL allows it to attempt to lock to the current settings of the multiplier and divider values.
Connecting the PLL causes the processor and all chip functions to run from the PLL
output clock. Changes to the PLLCON register do not take effect until a correct PLL feed
sequence has been given (see Section 3.8.7 “
PLL Feed register (PLLFEED -
0xE01F C08C)” and Section 3.8.3 “PLL Configuration register (PLLCFG - 0xE01F C084)”
on page 27).
Fig 9. PLL block diagram
CD
/2P
CLOCK
SYNCHRONIZATION
PD
CCLK
PLLC
PLOCK
F
OSC
PLLE
PHASE-
FREQUENCY
DETECTOR
bypass
MSEL[4:0]
CD
MSEL<4:0>
F
OUT
DIV-BY-M
CCO
F
CCO
0
0
PSEL[1:0]
direct
1
0
0
1
0
1
PD
PD