Philips LPC2101 - PLL Configuring Examples; Procedure for Determining PLL Settings

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 30
Philips Semiconductors
UM10161
Volume 1 Chapter 3: System control block
The PLL inputs and settings must meet the following:
• F
OSC
is in the range of 10 MHz to 25 MHz.
• CCLK is in the range of 10 MHz to F
max
(the maximum allowed frequency for the
microcontroller - determined by the system microcontroller is embedded in).
• F
CCO
is in the range of 156 MHz to 320 MHz.
3.8.10 Procedure for determining PLL settings
If a particular application uses the PLL, its configuration may be determined as follows:
1. Choose the desired processor operating frequency (CCLK). This may be based on
processor throughput requirements, need to support a specific set of UART baud
rates, etc. Bear in mind that peripheral devices may be running from a lower clock
than the processor (see Section 3.11 “
APB divider” on page 36).
2. Choose an oscillator frequency (F
OSC
). CCLK must be the whole (non-fractional)
multiple of F
OSC
.
3. Calculate the value of M to configure the MSEL bits. M = CCLK / F
OSC
. M must be in
the range of 1 to 32. The value written to the MSEL bits in PLLCFG is M − 1 (see
Tabl e 2 3
.
4. Find a value for P to configure the PSEL bits, such that F
CCO
is within its defined
frequency limits. F
CCO
is calculated using the equation given above. P must have one
of the values 1, 2, 4, or 8. The value written to the PSEL bits in PLLCFG is 00 for
P = 1; 01 for P = 2; 10 for P = 4; 11 for P = 8 (see Ta bl e 22
).
3.8.11 PLL configuring examples
Example: an application configuring the PLL
System design asks for F
OSC
= 10 MHz and requires CCLK = 60 MHz.
Table 22: PLL Divider values
PSEL Bits (PLLCFG bits [6:5]) Value of P
00 1
01 2
10 4
11 8
Table 23: PLL Multiplier values
MSEL Bits (PLLCFG bits [4:0]) Value of M
00000 1
00001 2
00010 3
00011 4
... ...
11110 31
11111 32