Philips LPC2101 - Interrupt Enable Clear Register (Vicintenclear - 0 Xffff F014); Interrupt Enable Register; Interrupt Select Register (Vicintselect - 0 Xffff F00 C)

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 49
Philips Semiconductors
UM10161
Volume 1 Chapter 5: VIC
5.4.5 Interrupt Enable Clear register (VICIntEnClear - 0xFFFF F014)
This is a write only register. This register allows software to clear one or more bits in the
Interrupt Enable register (see Section 5.4.4 “
Interrupt Enable register (VICIntEnable -
0xFFFF F010)” on page 48), without having to first read it.
5.4.6 Interrupt Select register (VICIntSelect - 0xFFFF F00C)
This is a read/write accessible register. This register classifies each of the 32 interrupt
requests as contributing to FIQ or IRQ.
Table 43: Interrupt Enable register (VICIntEnable - address 0xFFFF F010) bit description
Bit Symbol Description Reset
value
31:0 See
VICIntEnable
bit allocation
table.
When this register is read, 1s indicate interrupt requests or software interrupts
that are enabled to contribute to FIQ or IRQ.
When this register is written, ones enable interrupt requests or software
interrupts to contribute to FIQ or IRQ, zeroes have no effect. See Section 5.4.5
“Interrupt Enable Clear register (VICIntEnClear - 0xFFFF F014)” on page 49
and Ta bl e 4 5 below for how to disable interrupts.
0
Table 44: Software Interrupt Clear register (VICIntEnClear - address 0xFFFF F014) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol ----TIMER3TIMER2--
Access WO WO WO WO WO WO WO WO
Bit 23 22 21 20 19 18 17 16
Symbol ----I2C1AD0-EINT2
Access WO WO WO WO WO WO WO WO
Bit 15 14 13 12 11 10 9 8
Symbol EINT1 EINT0 RTC PLL SSP/SPI1 SPI0 I2C0 -
Access WO WO WO WO WO WO WO WO
Bit 7 6 5 4 3 2 1 0
Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 - WDT
Access WO WO WO WO WO WO WO WO
Table 45: Software Interrupt Clear register (VICIntEnClear - address 0xFFFF F014) bit description
Bit Symbol Value Description Reset
value
31:0 See
VICIntEnClear
bit allocation
table.
0 Writing a 0 leaves the corresponding bit in VICIntEnable
unchanged.
0
1 Writing a 1 clears the corresponding bit in the Interrupt Enable
register, thus disabling interrupts for this request.
Table 46: Interrupt Select register (VICIntSelect - address 0xFFFF F00C) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol ----TIMER3TIMER2--
Access R/W R/W R/W R/W R/W R/W R/W R/W