© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 82
9.1 Features
• 16 byte Receive and Transmit FIFOs
• Register locations conforming to ‘550 industry standard
• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
• Built-in fractional baud rate generator with autobauding capabilities.
• Mechanism that enables software and hardware flow control implementation
9.2 Pin description
9.3 Register description
UART0 contains registers organized as shown in Tab le 8 1. The Divisor Latch Access Bit
(DLAB) is contained in U0LCR[7] and enables access to the Divisor Latches.
UM10161
Chapter 9: Universal Asynchronous Receiver/Transmitter 0
(UART0)
Rev. 01 — 12 January 2006 User manual
Table 80: UART0 pin description
Pin Type Description
RXD0 Input Serial Input. Serial receive data.
TXD0 Output Serial Output. Serial transmit data.