Philips LPC2101 - Page 83

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© Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006 83 Philips Semiconductors
UM10161
Volume 1 Chapter 9: UART0
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Table 81: UART0 register map
Name Description Bit functions and addresses Access Reset
value
[1]
Address
MSB LSB
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
U0RBR Receiver Buffer
Register
8-bit Read Data RO NA 0xE000 C000
(DLAB=0)
U0THR Transmit Holding
Register
8-bit Write Data WO NA 0xE000 C000
(DLAB=0)
U0DLL Divisor Latch LSB 8-bit Data R/W 0x01 0xE000 C000
(DLAB=1)
U0DLM Divisor Latch MSB 8-bit Data R/W 0x00 0xE000 C004
(DLAB=1)
U0IER Interrupt Enable
Register
------En.ABTOEn.ABEO R/W 0x00 0xE000 C004
(DLAB=0)
-----En.RX
Lin.St.Int
Enable
THRE Int
En.RX
Dat.Av.Int
U0IIRInterrupt ID Reg.------ABTO IntABEO Int RO 0x01 0xE000 C008
FIFOs Enabled - - IIR3 IIR2 IIR1 IIR0
U0FCR FIFO Control
Register
RX Trigger - - - TX FIFO
Reset
RX FIFO
Reset
FIFO
Enable
WO 0x00 0xE000 C008
U0LCR Line Control
Register
DLAB Set
Break
Stick
Parity
Even
Par.Selct.
Parity
Enable
No. of
Stop Bits
Word Length Select R/W 0x00 0xE000 C00C
U0LSR Line Status
Register
RX FIFO
Error
TEMT THRE BI FE PE OE DR RO 0x60 0xE000 C014
U0SCR Scratch Pad Reg. 8-bit Data R/W 0x00 0xE000 C01C
U0ACR Auto-baud Control
Register
------ABTO
Int.Clr
ABEO
Int.Clr
R/W 0x00 0xE000 C020
-----Aut.Rstrt.ModeStart
U0FDR Fractional Divider
Register
Reserved[31:8] 0x10 0xE000 C028
MulVal DivAddVal
U0TERTX. Enable Reg.TXEN-------R/W0x800xE000C030