Philips LPC2101 - Interrupt Register (IR TIMER2: T2 IR -; Timer Control Register (TCR, TIMER2: T2 TCR - 0 Xe007 0004 and TIMER3: T3 TCR - 0 Xe007 4004)

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 203
Philips Semiconductors
UM10161
Volume 1 Chapter 16: Timer2 and Timer3
[1] Reset value reflects the data stored in used bits00 only. It does not include reserved bits content.
16.5.1 Interrupt Register (IR TIMER2: T2IR - 0xE007 0000 and TIMER3: T3IR -
0xE007 4000)
The Interrupt Register consists of four bits for the match interrupts and four bits for the
capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be
HIGH. Otherwise, the bit will be LOW. Writing a logic one to the corresponding IR bit will
reset the interrupt. Writing a zero has no effect.
16.5.2 Timer Control Register (TCR, TIMER2: T2TCR - 0xE007 0004 and
TIMER3: T3TCR - 0xE007 4004)
The Timer Control Register (TCR) is used to control the operation of the Timer/Counter.
EMR External Match Register. The EMR controls the
external match pins MAT2.2..0 and MAT3.3..0.
Note: MAT2.3 is not connected to a pin on
LPC2101/02/03.
R/W 0 0xE007 003C
T2EMR
0xE007 403C
T3EMR
CTCR Count Control Register. The CTCR selects between
Timer and Counter mode, and in Counter mode
selects the signal and edge(s) for counting.
R/W 0 0xE007 0070
T2CTCR
0xE007 4070
T3CTCR
PWMCON PWM Control Register. The PWMCON enables
PWM mode for the external match pins MAT2.3..0
and MAT3.3..0.
R/W 0 0xE007 0074
PWM0CON
0xE007 4074
PWM1CON
Table 175: TIMER/COUNTER2 and TIMER/CT3OUNTER3 register map
Generic
Name
Description Access Reset
value
[1]
TIMER/
COUNTER2
Address &
Name
TIMER/
COUNTER3
Address &
Name
Table 176: Interrupt Register (IR, TIMER2T2: T2IR - address 0xE007 0000 and TIMER3: T3IR - address 0xE007 4000)
bit description
Bit Symbol Description Reset value
0 MR0 Interrupt Interrupt flag for match channel 0. 0
1 MR1 Interrupt Interrupt flag for match channel 1. 0
2 MR2 Interrupt Interrupt flag for match channel 2. 0
3 MR3 Interrupt Interrupt flag for match channel 3. 0
4 CR0 Interrupt Interrupt flag for capture channel 0 event. 0
5 CR1 Interrupt Interrupt flag for capture channel 1 event. 0
6 CR2 Interrupt Interrupt flag for capture channel 2 event. 0
7 CR3 Interrupt Interrupt flag for capture channel 3 event.
Note: CAPn.3 not usable on Timer 2/Timer3
0