© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 183
Philips Semiconductors
UM10161
Volume 1 Chapter 14: A/D converter
14.4.2 A/D Global Data Register (AD0GDR - 0xE003 4004)
26:24 START
000
When the BURST bit is 0, these bits control whether and when an A/D conversion is
started:
No start (this value should be used when clearing PDN to 0).
0
001 Start conversion now.
010 Start conversion when the edge selected by bit 27 occurs on P0.16/EINT0/MAT0.2 pin.
011 Start conversion when the edge selected by bit 27 occurs on P0.22.
100 Start conversion when the edge selected by bit 27 occurs on MAT0.1.
101 Start conversion when the edge selected by bit 27 occurs on MAT0.3.
110 Start conversion when the edge selected by bit 27 occurs on MAT1.0.
111 Start conversion when the edge selected by bit 27 occurs on MAT1.1.
27 EDGE
1
This bit is significant only when the START field contains 010-111. In these cases:
Start conversion on a falling edge on the selected CAP/MAT signal.
0
0 Start conversion on a rising edge on the selected CAP/MAT signal.
31:28 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 159: A/D Control Register (AD0CR - address 0xE003 4000 ) bit description
Bit Symbol Value Description Reset
value
Table 160: A/D Global Data Register (AD0GDR - address 0xE003 4004 ) bit description
Bit Symbol Description Reset
value
5:0 - Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
NA
15:6 RESULT When DONE is 1, this field contains a binary fraction representing the voltage on
the Ain pin selected by the SEL field, divided by the voltage on the V
DDA
pin
(V/V
REF
). Zero in the field indicates that the voltage on the Ain pin was less than,
equal to, or close to that on V
SSA
, while 0x3FF indicates that the voltage on Ain was
close to, equal to, or greater than that on V
REF
.
NA
23:16 - Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
NA
26:24 CHN These bits contain the channel from which the RESULT bits were converted (e.g.
000 identifies channel 0, 001 channel 1...).
NA
29:27 - Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
NA
30 OVERUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost
and overwritten before the conversion that produced the result in the RESULT bits.
This bit is cleared by reading this register.
0
31 DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this
register is read and when the ADCR is written. If the ADCR is written while a
conversion is still in progress, this bit is set and a new conversion is started.
0
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