© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 21
Philips Semiconductors
UM10161
Volume 1 Chapter 3: System control block
3.5.4 External Interrupt Mode register (EXTMODE - 0xE01F C148)
The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pins
that are selected for the EINT function (see Section7.4 on page66
) and enabled via the
VICIntEnable register (see Section 5.4.4 on page 48
) can cause interrupts from the
External Interrupt function (though of course pins selected for other functions may cause
interrupts from those functions).
Note: Software should only change a bit in this register when its interrupt is
disabled in the VICIntEnable register, and should write the corresponding 1 to the
EXTINT register before enabling (initializing) or re-enabling the interrupt, to clear
the EXTINT bit that could be set by changing the mode.
3.5.5 External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)
In level-sensitive mode, the bits in this register select whether the corresponding pin is
high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or
falling-edge sensitive. Only pins that are selected for the EINT function (see Section 7.4
on page 66) and enabled in the VICIntEnable register (see Section 5.4.4 on page 48) can
cause interrupts from the External Interrupt function (though of course pins selected for
other functions may cause interrupts from those functions).
Note: Software should only change a bit in this register when its interrupt is
disabled in the VICIntEnable register, and should write the corresponding 1 to the
EXTINT register before enabling (initializing) or re-enabling the interrupt, to clear
the EXTINT bit that could be set by changing the polarity.
2 EXTWAKE2 When one, assertion of EINT2 will wake up the processor from
Power-down mode.
0
14:3 - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
NA
15 RTCWAKE When one, assertion of an RTC interrupt will wake up the
processor from Power-down mode.
0
Table 10: Interrupt Wake-up register (INTWAKE - address 0xE01F C144) bit description
Bit Symbol Description Reset
value
Table 11: External Interrupt Mode register (EXTMODE - address 0xE01F C148) bit
description
Bit Symbol Value Description Reset
value
0 EXTMODE0 0 Level-sensitivity is selected for EINT0. 0
1 EINT0 is edge sensitive.
1 EXTMODE1 0 Level-sensitivity is selected for EINT1. 0
1 EINT1 is edge sensitive.
2 EXTMODE2 0 Level-sensitivity is selected for EINT2. 0
1 EINT2 is edge sensitive.
7:3 - - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
NA
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