© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 174
Philips Semiconductors
UM10161
Volume 1 Chapter 13: SSP
13.3.9 Setup and hold time requirements on CS with respect to SK in
Microwire mode
In the Microwire mode, the SSP slave samples the first bit of receive data on the rising
edge of SK after CS has gone LOW. Masters that drive a free-running SK must ensure
that the CS signal has sufficient setup and hold margins with respect to the rising edge of
SK.
Figure 48
illustrates these setup and hold time requirements. With respect to the SK rising
edge on which the first bit of receive data is to be sampled by the SSP slave, CS must
have a setup of at least two times the period of SK on which the SSP operates. With
respect to the SK rising edge previous to this edge, CS must have a hold of at least one
SK period.
13.4 Register description
The SSP contains 9 registers as shown in Ta bl e 1 4 7. All registers are byte, half word and
word accessible.
Fig 47. Microwire frame format (continuos transfers)
SK
CS
SO
SI
MSB LSB
4 to 16 bits
output data
8 bit control
4 to 16 bits
output data
MSB LSB
0
MSB LSB
LSB
Fig 48. Microwire frame format (continuos transfers) - details
SK
CS
SI
t
HOLD
= t
SK
t
SETUP
=2*t
SK
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