Philips LPC2101 - Page 199

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 199
Philips Semiconductors
UM10161
Volume 1 Chapter 15: Timer0 and Timer1
(1) The capture register 3 (CAP0.3) is not available on TIMER0.
Fig 52. Timer0/1 block diagram
reset
MAXVAL
TIMER CONTROL REGISTER PRESCALE REGISTER
PRESCALE COUNTER
PCLK
enable
CAPTURE REGISTER 3
(1)
CAPTURE REGISTER 2
CAPTURE REGISTER 1
CAPTURE REGISTER 0
MATCH REGISTER 3
MATCH REGISTER 2
MATCH REGISTER 1
MATCH REGISTER 0
CAPTURE CONTROL REGISTER
CONTROL
TIMER COUNTER
CSN
TCI
CE
=
=
=
=
INTERRUPT REGISTER
EXTERNAL MATCH REGISTER
MATCH CONTROL REGISTER
MAT[3:0]
INTERRUPT
CAP[3:0]
STOP ON MATCH
RESET ON MATCH
LOAD[3:0]