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General| Processor Type | Dual-core ARM Cortex-A7 |
|---|---|
| Clock Speed | 1.0 GHz |
| GPU | Mali-400 MP2 |
| Operating System Support | Android, Linux |
| Process | 40nm |
| RAM Support | DDR3/DDR3L |
| Video Output | HDMI |
| Video Decoding | H.264, MPEG-1/2/4 |
| Video Encoding | H.264 |
| USB | USB |
| Ethernet | 10/100 Mbps |
| Storage | NAND Flash |
Details the Allwinner A20 processor, a dual-core ARM Cortex-A7 mobile application solution.
Presents the block diagram of the A20 processor, illustrating its main components and interconnections.
Details the memory mapping of the A20 chip, including areas, addresses, and sizes for various modules.
Provides information on CPU configuration features, including software reset control and idle counters.
Describes the Clock Control Unit (CCU), its features, and clock domains.
Details the system boot process from various sources like NAND Flash, SD card, and USB.
Explains the system control features, including internal SRAM mapping and version register.
Details the Pulse Width Modulation (PWM) signals used for LCD contrast and brightness control.
Describes the timer functionalities, including scheduler interrupts, watchdog, and real-time clock.
Provides an overview of the High Speed Timer, its channels, and clock sources.
Details the Generic Interrupt Controller (GIC) and its interrupt sources.
Explains the Direct Memory Access (DMA) controller, its types, and capabilities.
Describes the embedded high-quality stereo audio codec with headphone amplifier.
Details the LRADC, which is a 6-bit resolution ADC for key application.
Describes the TP controller, a 4-wire resistive touch screen controller with 12-bit A/D converter.
Explains the Security System (SS), an encrypt/decrypt function accelerator.
Details the authentication module for security JTAG, including EFUSE field bits.
Describes the on-chip EFUSE providing electrical fuses for security application.
Details the Port Controller, its ports, and configuration options.
Describes the DRAM Controller (DRAMC) and its features, supporting DDR2 and DDR3 SDRAM.
Details the NFC (NAND Flash Controller) supporting various NAND/MLC flash memory types.
Details the mixer processor in A20, including its features and register list.
Describes the CSI0 module features, including input data, protocols, and data paths.
Details the CSI1 module features, input data formats, and protocols.
Describes the TCON features, supporting dual-channel LCD output and various interfaces.
Details the basic video and audio features of the HDMI interface.
Explains the DEFE features: image capture, scaling, format conversion, and color space conversion.
Describes the DEBE features, including layers, alpha blending, color key, and scaling.
Details the TV decoder features, supporting CVBS NTSC/PAL and YPbPr formats.
Describes the SD/MMC controller features, supporting various standards and modes.
Details the TWI interface, its features, and operation modes.
Explains the SPI module features, including buffers, modes, and clock sources.
Describes the UART features, including modes, FIFOs, and interrupt support.
Details the PS2 module, its Dual-Role controller capabilities, and features.
Explains the CIR (Consumer IR) interface for remote control via infra-red light.
Describes the USB DRD, a Dual-Role Device controller supporting various speeds.
Details the USB Host controller compliance, features, and HCI controllers.
Explains the Digital Audio Interface, configurable as I2S or PCM, and its features.
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