Allwinner A20 - Audio Codec Register Description

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 173 / 812
Register Name
Offset
Description
AC_DAC_FIFOS
0x08
DAC FIFO Status Register
AC_DAC_TXDATA
0x0C
DAC TX Data Register
AC_DAC_ACTL
0x10
DAC Analog Control Register
AC_DAC_TUNE
0x14
DAC/ ADC Performance Tuning Register
AC_ADC_FIFOC
0x1C
ADC FIFO Control Register
AC_ADC_FIFOS
0x20
ADC FIFO Status Register
AC_ADC_RXDATA
0x24
ADC RX Data Register
AC_ADC_ACTL
0x28
ADC Analog Control Register
AC_DAC_CNT
0x30
DAC TX FIFO Counter Register
AC_ADC_CNT
0x34
ADC RX FIFO Counter Register
AC_SYS_VERI
0x38
System Calibration Verify Register
AC_MIC_PHONE_CAL
0x3c
MIC gain & Phone out Control Register
1.13.4. Audio Codec Register Description
1.13.4.1. DAC DIGITAL PART CONTROL REGISTER
Offset: 0x00
Register Name: AC_DAC_DPC
Bit
Read/Write
Default
Description
31
R/W
0x0
EN_DA.
DAC Digital Part Enable
0: Disable
1: Enable
30:29
/
/
/
28:25
R/W
0x0
MODQU.
Internal DAC Quantization Levels
Levels=[7*(21+MODQU[3:0])]/128
Default levels=7*21/128=1.15
24
R/W
0x0
DWA.
DWA Function Disable
0: Enable
1: Disable