Allwinner A20 - Page 174

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 174 / 812
Offset: 0x00
Register Name: AC_DAC_DPC
Bit
Read/Write
Default
Description
23:19
/
/
/
18
R/W
0x0
HPF_EN.
High Pass Filter Enable
0: Disable
1: Enable
17:12
R/W
0x0
DVOL.
Digital volume control: dvc, ATT=(DVC[5:0]-2)*(-1.16dB)
62 steps, -1.16dB/step
11:0
/
/
/
1.13.4.2. DAC FIFO CONTROL REGISTER
Offset: 0x4
Register Name: AC_DAC_FIFOC
Bit
Read/Write
Default
Description
31:29
R/W
0x0
DAC_FS.
Sample Rate of DAC
000: 48KHz
010: 24KHz
100: 12KHz
110: 192KHz
001: 32KHz
011: 16KHz
101: 8KHz
111: 96KHz
44.1KHz/22.05KHz/11.025KHz can be supported by Audio
PLL Configure Bit
28
R/W
0x0
FIR Version
0: 64-Tap FIR
1: 32-Tap FIR
27
/
/
/
26
R/W
0x0
SEND_LASAT.
Audio sample select when TX FIFO under run
0: Sending zero
1: Sending last audio sample