Allwinner A20 - CPUCFG Register Description

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 25 / 812
1.4.3. CPUCFG Register Description
1.4.3.1. CPU0 RESET CONTROL(DEFAULT: 0X00000003)
Offset: 0x40
Register Name: CPU0_RST_CTRL
Bit
Read/
Write
Default/Hex
Description
31:2
/
/
/.
1
R/W
0x1
CPU0_CORE_REST.
These are the primary reset signals which initialize the
processor logic in the processor power domains, not including
the debug, breakpoint and watchpoint logic.
0: assert
1: de-assert.
0
R/W
0x1
CPU0_RESET.
CPU0 Reset Assert.
These power-on reset signals initialize all the processor logic,
including CPU Debug, and breakpoint and watch point logic in
the processor power domains. They do not reset debug logic
in the debug power domain.
0: assert
1: de-assert.
1.4.3.2. CPU0 CONTROL REGISTER(DEFAULT :0X00000000)
Offset: 0x44
Register Name: CPU0_CTRL_REG
Bit
Read/
Write
Default/Hex
Description
31:1
/
/
/
0
R/W
0x0
CPU0_CP15_WRITE_DISABLE.
Disable write access to certain CP15 registers.
0: enable
1: disable