Allwinner A20 - PS2 Special Requirements

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 641 / 812
Offset: 0x0018
Register Name: PS2_CKDR
Default Value: 0x0000_2F4F
Bit
Read/Write
Default
Description
PS2 Clock Divider Factor (PCDF)
PCDF = SAMPLE_CLK /PS2_CLK – 1 = 1MHz/PS2_CLK - 1
The frequency of PS2_CLK must be in the range 10-16.7KHz.
Note: This factor is used in device mode only.
6.5.6. PS2 Special Requirements
6.5.6.1. PS2 INTERFACE PIN LIST
Port Name
Width
Direction
Description
PS2_CLK
1
IN/OUT
PS2 clock signal
PS2_DATA
1
IN/OUT
PS2 data signal
6.5.6.2. PS2 CLOCK REQUIREMENT
Clock Name
Description
Requirement
apb_clk
APB bus clock
>=1MHz