Allwinner A20 - DEBE Register Description

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 532 / 812
5.4.4. DEBE Register Description
5.4.4.1. DE BACK-END MODE CONTROL REGISTER
Offset: 0x800
Register Name: DEBE_MODCTL_REG
Bit
Read/
Write
Default/
Hex
Description
31:30
/
/
/
29
R/W
0
LINE_SEL
Start top/bottom line selection in interlace mode
28
R/W
0
ITLMOD_EN
Interlace mode enable
0:disable
1:enable
27
/
/
/
22:20
R/W
0
OUT_SEL
Output selection
000:LCD
110:FE0 only
111:FE1 only
Other: reserved
19:17
/
/
/
16
R/W
0
HWC_EN
Hardware cursor enabled/disabled control
0: Disabled
1: Enabled
Hardware cursor has the highest priority, in the alpha blender0, the
alpha value of cursor will be selected
15:12
/
/
/
11
R/W
0
LAY3_EN
Layer3 Enable/Disable
0: Disabled
1: Enabled
10
R/W
0
LAY2_EN
Layer2 Enable/Disable
0: Disabled
1: Enabled