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Allwinner A20 - SPI Register Description

Allwinner A20
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A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 592 / 812
Register Name
Offset
Description
SPI_TC
0x24
SPI Transmit Counter Register
SPI_FIFO_STA
0x28
SPI FIFO Status register
6.3.4. SPI Register Description
6.3.4.1. SPI RX DATA REGISTER
Offset: 0x00
Register Name: SPI_RXDATA
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:0
R
0
RDATA
Receive Data
In 8-bits SPI bus width, this register can be accessed in byte,
half-word or word unit by AHB. In byte accessing method, if
there are words in RXFIFO, the top word is returned and the
RXFIFO depth is decreased by 1. In half-word accessing
method, the two SPI bursts are returned and the RXFIFO
depth is decrease by 2. In word accessing method, the four
SPI bursts are returned and the RXFIFO depth is decreased
by 4.
6.3.4.2. SPI TX DATA REGISTER
Offset: 0x04
Register Name: SPI_TXDATA
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:0
W
0
TDATA
Transmit Data

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