Allwinner A20 - 2.1. DRAM

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2.1. DRAM

2.1.1. Overview

The DRAM Controller (DRAMC) provides a simple, flexible, burst-optimized interface to all

in-dusty-standard double data rate II (DDR2) ordinary SDRAM andouble data rate III (DDR3) ordinary

SDRAM. It supports up to a 16G bits memory address space.

The DRAMC automatically handles memory management, initialization, and refresh operations. It

gives the host CPU a simple command interface, hiding details of the required address, page, and

burst handling procedures. All memory parameters are runtime-configurable, including timing,

memory setting, SDRAM type, and Extended-Mode-Register settings.

It features:

 Support DDR3L/DDR3/DDR2 SDRAM

 Support different memory device’s power of 1.35V,1.5V and 1.8V

 Support memory capacity up to 16G bits (2GB)

 16 address signal lines and 3 bank signal lines

 Data IO size can up to 32-bit for DDR2 and DDR3 (x8, x16)

 Automatically generates initialization and refresh sequences

 Runtime-configurable parameters setting for application flexibility

 Clock frequency can be chosen for different applications

 Priority of transferring through multiple ports is programmable



Random read or write operations