Allwinner A20 - Transport Stream Clock Requirement

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 768 / 812
Offset: TSD+0x20
Register Name: TSD_CWR
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
value
6.13.5. Transport Stream Clock Requirement
Clock Name
Description
Requirement
HCLK
AHB bus clock
TS_CLK
Clock of TS Stream in SPI
mode
TSC_CLK
TS serial clock from CCU
TSC_CLK >=16*TS_CLK