Allwinner A20 - 6.3. SPI

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6.3. SPI

6.3.1. Overview

The SPI allows rapid data communication with fewer software interrupts. The SPI module contains

one 64x8 receiver buffer (RXFIFO) and one 64x8 transmit buffer (TXFIFO). It can work at two modes:

Master mode and Slave mode.

It features:

 Support industry-standard AMBA High-Performance Bus (AHB) and it is fully compliant with the

AMBA Specification, Revision 2.0. Supports 32-bit Little Endian bus.

 Support AMBA AHB Slave mode

 Full-duplex synchronous serial interface

 Master/Slave configurable

 Four chip selects to support multiple peripherals for SPI0 and SPI1 has one chip select

 8-bit wide by 64-entry FIFO for both transmit and receive data

 Polarity and phase of the Chip Select (SPI_SS) and SPI Clock (SPI_SCLK) are configurable

 Support dedicated DMA