Allwinner A20 - TP Register Description

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 207 / 812
Register Name
Offset
Description
TP_CDAT
0x1c
TP Common Data
TEMP_DATA
0x20
Temperature Data Register
TP_DATA
0x24
TP Data Register
TP_IO_CONFIG
0x28
TP IO Configuration
TP_PORT_DATA
0x2c
TP IO Port Data
1.15.7. TP Register Description
1.15.7.1. TP CONTROL REGISTER 0
Offset: 0x00
Register Name: TP_CTRL0
Bit
Read/
Write
Default
/Hex
Description
31:24
R/W
0xF
ADC_FIRST_DLY.
ADC First Convert Delay Time(T_FCDT)setting
Based on ADC First Convert Delay Mode select (Bit 23)
T_FCDT = ADC_FIRST_DLY * ADC_FIRST_DLY_MODE
23
R/W
0x1
ADC_FIRST_DLY_MODE.
ADC First Convert Delay Mode Select
0: CLK_IN/16
1: CLK_IN/16*256
22
R/W
0x0
ADC_CLK_SELECT.
ADC Clock Source Select:
0: HOSC(24MHZ)
1: Audio PLL
21:20
R/W
0x0
ADC_CLK_DIVIDER.
ADC Clock Divider(CLK_IN)
00: CLK/2
01: CLK/3
10: CLK/6
11: CLK/1