Allwinner A20 - HDMI Block Diagram; HDMI Control Register Description

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 437 / 812
5.2.2. HDMI Block Diagram
Video Capture
Control REG
&
State Machine
Audio Capture
&
FIFO
Control Packet
&
Aux Packet
MUX
TMDS
TX
2X/4X
Pixel Repeater
Interrupt
Logic
DDC
VS
HS
D[23:0]
AHB
DMA
SCL
SDA
TX2P/M
TX1P/M
TX0P/M
TXCP/M
HPD
5.2.3. HDMI Control Register Description
Module Name
Base Address
HDMI
0x01C16000
Base address:
Register Name
Offset
Description
Version_ID
0x000
Version ID register
Ctrl
0x004
System control register
Int_Status
0x008
Interrupt register
HPD
0x00c
HDMI hot plug detect register
VID_Ctrl
0x010
Video control register
VID_Timing_0
0x014
Video timing register 0