Allwinner A20 - Page 438

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 438 / 812
Register Name
Offset
Description
VID_Timing_1
0x018
Video timing register 1
VID_Timing_2
0x01c
Video timing register 2
VID_Timing_3
0x020
Video timing register 3
VID_Timing_4
0x024
Video timing register 4
Aud_Ctrl
0x040
Audio control register
ADMA_Ctrl
0x044
Audio DMA&FIFO control register
Aud_Fmt
0x048
Audio Format control register
Aud_PCM_Ctrl
0x04c
Audio PCM control register
Aud_CTS
0x050
ACR CTS
Aud_N
0x054
ACR N
Aud_CH_Status0
0x058
Audio channel Status register 0
Aud_CH_Status1
0x05c
Audio channel Status register 1
AVI_Info_Pkt
0x080
AVI Info Frame
Aud_info_Pkt
0x0a0
Audio Info Frame
ACP_Pkt
0x0c0
ACP packet
GP_Pkt
0x0e0
General Control Packet
Pad Ctrl0
0x200
PLL/DRV Setting 0
Pad Ctrl1
0x204
PLL/DRV Setting 1
PLL_Ctrl
0x208
PLL/DRV Setting 2
PLL_Dbg0
0x20c
PLL/DRV Setting 3
PLL_Dbg1
0x210
PLL/DRV Setting 4
HPD_CEC
0x214
PLL/DRV Setting 5
SPD_Pkt
0x240
SPD packet
Pkt_Ctrl0
0x2f0
PACKET_CONTROL0
Pkt_Ctrl0
0x2f4
PACKET_CONTROL1
HDMI_DBG4
0x310
Audio sample counter
Aud_TX_FIFO
0x400
Audio Normal DMA Port
DDC_Ctrl
0x500
DDC Control Register
DDC_Slave_Addr
0x504
DDC Slave Address Register
DDC_Int_Mask
0x508
DDC Interrupt Mask Register
DDC_Int_Status
0x50C
DDC Interrupt Status Register
DDC_FIFO _Ctrl
0x510
DDC FIFO Control Register