Allwinner A20 - 6.2. TWI

To Next Page

To Previous Page

6.2. TWI

6.2.1. Overview

The TWI is designed to be used as an interface between CPU host and the serial 2-Wire bus. It can

support all standard 2-Wire transfer, including Slave and Master. The communication to the 2-Wire bus is

carried out on a byte-wise basis using interrupt or polled handshaking. This TWI can be operated in

standard mode (100K bps) or fast-mode, supporting data rate up to 400K bps. Multiple Masters and 10-bit

addressing Mode are supported for this specified application. General Call Addressing is also supported

in Slave mode.

The TWI features:

 Support industry-standard AMBA Peripheral Bus (APB) and it is fully compliant with the AMBA

Specification, Revision 2.0.

 Software-programmable for Slave or Master

 Support Repeated START signal

 Support multi-master systems

 Allow 10-bit addressing with 2-Wire bus

 Perform arbitration and clock synchronization

 Own address and General Call address detection

 Interrupt on address detection

 Support speed up to 400Kbits/s (‘fast mode’)

 Allow operation from a wide range of input clock frequencies