Allwinner A20 - Port Register List

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 238 / 812
Port I(PI)
Multiplex Function Select
PI6
SDC3_D0
PI7
SDC3_D1
PI18
SDC3_D2
PI19
SDC3_D3
PI10
SPI0_CS0
UART5_TX
EINT22
PI11
SPI0_CLK
UART5_RX
EINT23
PI12
SPI0_MOSI
UART6_TX
CLK_OUT_A
EINT24
PI13
SPI0_MISO
UART6_RX
CLK_OUT_B
EINT25
PI14
SPI0_CS1
PS2_SCK1
TCLKIN0
EINT26
PI15
SPI1_CS1
PS2_SDA1
TCLKIN1
EINT27
PI16
SPI1_CS0
UART2_RTS
EINT28
PI17
SPI1_CLK
UART2_CTS
EINT29
PI18
SPI1_MOSI
UART2_TX
EINT30
PI19
SPI1_MISO
UART2_RX
EINT31
PI20
PS2_SCK0
UART7_TX
HSCL
PI21
PS2_SDA0
UART7_RX
HSDA
Port I(PI) Multiplex Function Select Table
1.19.3. Port Register List
Module Name
Base Address
PIO
0x01C20800
Register Name
Offset
Description
Pn_CFG0
n*0x24+0x00
Port n Configure Register 0 (n from 0 to 8)
Pn_CFG1
n*0x24+0x04
Port n Configure Register 1 (n from 0 to 8)
Pn_CFG2
n*0x24+0x08
Port n Configure Register 2 (n from 0 to 8)
Pn_CFG3
n*0x24+0x0C
Port n Configure Register 3 (n from 0 to 8)
Pn_DAT
n*0x24+0x10
Port n Data Register (n from 0 to 8)