Allwinner A20 - CSI0 Block Diagram; CSI0 Description

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4.1.2. CSI0 Block Diagram

CSI

Control

Module

System BUS

FIFO 2

FIFO 1

FIFO 0

DMA

irq

CS Data[7:0]/Data[15:0]

CS Data Clock

CS Hsync

CS Vsync

Channel 0

Channel 1

Channel 2

Channel 3

4.1.3. CSI0 Description

4.1.3.1. CSI DATA PORTS

Bayer

YCbCr (YUV)

Interlaced

Pass-through

FIFO0

Red pixel data

Y pixel data

All field 1 pixel data

All pixel data

FIFO1

Green pixel data

Cb (U) pixel data

All field 2 pixel data

FIFO2

Blue pixel data

Cr (V) pixel data

4.1.3.2. TIMING DIAGRAM

CSI timing

Vref= positive; Href= positive