Allwinner A20 - Gmac; Overview

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6.12. GMAC

6.12.1. Overview

The GMAC controller enables a host to transmit and receive data over Ethernet in compliance with the

IEEE 802.3-2002 standard. It supports 10M/100M/1000M external PHY with RGMII interface in both full

and half duplex mode.

The GMAC-DMA is designed for packet-oriented data transfer based on a linked list of descriptors. 4KB

TXFIFO and 16KB RXFIFO are provided to keep continuous transmission and reception. Flow Control,

CRC Pad & Stripping, and address filtering are supported in this module as well.

It features:

 Support 10/100/1000-Mbps data transfer rates

 Support RGMII PHY interface

 Support both full-duplex and half-duplex operation

 Automatic CRC and pad generation controllable on a per-frame basis

 Options for Automatic Pad/CRC Stripping on receive frames

 Programmable frame length to support Standard or Jumbo Ethernet frames with sizes up to 16 KB

 Programmable Inter Frame Gap (40-96 bit times in steps of 8)

 Supports a variety of flexible address filtering modes

 Separate 32-bit status returned for transmission and reception packets

 Optimization for packet-oriented DMA transfers with frame delimiters

 Dual-buffer (ring) or linked-list (chained) descriptor chaining

 Descriptor architecture, allowing large blocks of data transfer with minimum CPU intervention; each

descriptor can transfer up to 4 KB data

 Comprehensive status report for normal operation and transfers with errors

 4KB TXFIFO for transmission packets and 16KB RXFIFO for reception packets

 Programmable interrupt options for different operational conditions