Allwinner A20 - Clock Tree Diagram; CCU Register List

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 35 / 812
1.5.2. Clock Tree Diagram
MUX
CPU0_1
InternalOSC
(32KHz+-20%)
ExternalOSC
MUX
X
LOSC
X
PLL6
MUX
/2
AHB_CLK_DIV_RATIO
(/1 /2 /4 /8)
AHB
APB0_CLK_RATIO
(/2 /2 /4 /8)
APB0
MUX
CLK_RAT_N
(/1 /2 /4 /8)
CLK_RAT_M
1/(1~32)
APB1
PLL1
AXI
AXI_CLK_DIV_RATIO
(1/(1~4))
32.768KHz
24MHz
L2 Cache
/1
System
ATB/APB
ATB_APB_CLK_DIV
(/1 /2 /4)
200MHz(Sourc
e from PLL6)
1.5.3. CCU Register List
Module Name
Base Address
CCU
0x01C20000
Register Name
Offset
Description
PLL1_CFG_REG
0x0000
PLL1 CONTROL
PLL1_TUN_REG
0x0004
PLL1 TUNING
PLL2_CFG_REG
0x0008
PLL2 CONTROL
PLL2_TUN_REG
0x000C
PLL2 TUNING