Allwinner A20 - DMA Controller Register Description

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 154 / 812
1.12.3. DMA Controller Register Description
1.12.3.1. DMA IRQ ENABLE REGISTER(DEFAULT: 0X00000000)
Offset: 0x0
Register Name: DMA_IRQ_EN_REG
Bit
Read/
Write
Default/He
x
Description
31
R/W
0x0
DDMA7_END_IRQ_EN.
Dedicated DMA 7 End Transfer Interrupt Enable.
0: Disable, 1: Enable.
30
R/W
0x0
DDMA7_HF_IRQ_EN.
Dedicated DMA 7 Half Transfer Interrupt Enable.
0: Disable, 1: Enable.
29
R/W
0x0
DDMA6_END_IRQ_EN.
Dedicated DMA 6 End Transfer Interrupt Enable.
0: Disable, 1: Enable.
28
R/W
0x0
DDMA6_HF_IRQ_EN.
Dedicated DMA 6 Half Transfer Interrupt Enable.
0: Disable, 1: Enable.
27
R/W
0x0
DDMA5_END_IRQ_EN.
Dedicated DMA 5 End Transfer Interrupt Enable.
0: Disable, 1: Enable.
26
R/W
0x0
DDMA5_HF_IRQ_EN
Dedicated DMA 5 Half Transfer Interrupt Enable.
0: Disable, 1: Enable.
25
R/W
0x0
DDMA4_END_IRQ_EN
Dedicated DMA 4 End Transfer Interrupt Enable.
0: Disable, 1: Enable.
24
R/W
0x0
DDMA4_HF_IRQ_EN
Dedicated DMA 4 Half Transfer Interrupt Enable.
0: Disable, 1: Enable.
23
R/W
0x0
DDMA3_END_IRQ_EN
Dedicated DMA 3 End Transfer Interrupt Enable.
0: Disable, 1: Enable.
22
R/W
0x0
DDMA3_HF_IRQ_EN
Dedicated DMA 3 Half Transfer Interrupt Enable.
0: Disable, 1: Enable.