Allwinner A20 - Page 155

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 155 / 812
Offset: 0x0
Register Name: DMA_IRQ_EN_REG
Bit
Read/
Write
Default/He
x
Description
21
R/W
0x0
DDMA2_END_IRQ_EN
Dedicated DMA 2 End Transfer Interrupt Enable.
0: Disable, 1: Enable.
20
R/W
0x0
DDMA2_HF_IRQ_EN
Dedicated DMA 2 Half Transfer Interrupt Enable.
0: Disable, 1: Enable.
19
R/W
0x0
DDMA1_END_IRQ_EN
Dedicated DMA 1 End Transfer Interrupt Enable.
0: Disable, 1: Enable.
18
R/W
0x0
DDMA1_HF_IRQ_EN
Dedicated DMA 1 Half Transfer Interrupt Enable.
0: Disable, 1: Enable.
17
R/W
0x0
DDMA0_END_IRQ_EN
Dedicated DMA 0 End Transfer Interrupt Enable.
0: Disable, 1: Enable.
16
R/W
0x0
DDMA0_HF_IRQ_EN
Dedicated DMA 0 Half Transfer Interrupt Enable.
0: Disable, 1: Enable.
15
R/W
0x0
NDMA7_END_IRQ_EN.
Normal DMA 7 End Transfer Interrupt Enable.
0: Disable, 1: Enable.
14
R/W
0x0
NDMA7_HF_IRQ_EN
Normal DMA 7 Half Transfer Interrupt Enable.
0: Disable, 1: Enable.
13
R/W
0x0
NDMA6_END_IRQ_EN
Normal DMA 6 End Transfer Interrupt Enable.
0: Disable, 1: Enable.
12
R/W
0x0
NDMA6_HF_IRQ_EN
Normal DMA 6 Half Transfer Interrupt Enable.
0: Disable, 1: Enable.
11
R/W
0x0
NDMA5_END_IRQ_EN
Normal DMA 5 End Transfer Interrupt Enable.
0: Disable, 1: Enable.