Allwinner A20 - Page 156

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 156 / 812
Offset: 0x0
Register Name: DMA_IRQ_EN_REG
Bit
Read/
Write
Default/He
x
Description
10
R/W
0x0
NDMA5_HF_IRQ_EN
Normal DMA 5 Half Transfer Interrupt Enable.
0: Disable, 1: Enable.
9
R/W
0x0
NDMA4_END_IRQ_EN
Normal DMA 4 End Transfer Interrupt Enable.
0: Disable, 1: Enable.
8
R/W
0x0
NDMA4_HF_IRQ_EN
Normal DMA 4 Half Transfer Interrupt Enable.
0: Disable, 1: Enable.
7
R/W
0x0
NDMA3_END_IRQ_EN
Normal DMA 3 End Transfer Interrupt Enable.
0: Disable, 1: Enable.
6
R/W
0x0
NDMA3_HF_IRQ_EN
Normal DMA 3 Half Transfer Interrupt Enable.
0: Disable, 1: Enable.
5
R/W
0x0
NDMA2_END_IRQ_EN
Normal DMA 2 End Transfer Interrupt Enable.
0: Disable, 1: Enable.
4
R/W
0x0
NDMA2_HF_IRQ_EN
Normal DMA 2 Half Transfer Interrupt Enable.
0: Disable, 1: Enable.
3
R/W
0x0
NDMA1_END_IRQ_EN
Normal DMA 1 End Transfer Interrupt Enable.
0: Disable, 1: Enable.
2
R/W
0x0
NDMA1_HF_IRQ_EN
Normal DMA 1 Half Transfer Interrupt Enable.
0: Disable, 1: Enable.
1
R/W
0x0
NDMA0_END_IRQ_EN
Normal DMA 0 End Transfer Interrupt Enable.
0: Disable, 1: Enable.
0
R/W
0x0
NDMA0_HF_IRQ_EN
Normal DMA 0 Half Transfer Interrupt Enable.
0: Disable, 1: Enable.