Allwinner A20 - Page 157

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 157 / 812
1.12.3.2. DMA IRQ PENDING STATUS REGISTER(DEFAULT: 0X00000000)
Offset: 0x4
Register Name: DMA_IRQ_PEND_STA_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
DDMA7_END_IRQ_PEND.
Dedicated DMA 7 End Transfer Interrupt Pending. Set 1 to the
bit will clear it.
0: No effect, 1: Pending.
30
R/W
0x0
DDMA7_HF_IRQ_PEND
Dedicated DMA 7 Half Transfer Interrupt Pending. Set 1 to the
bit will clear it.
0: No effect, 1: Pending.
29
R/W
0x0
DDMA6_END_IRQ_PEND
Dedicated DMA 6 End Transfer Interrupt Pending. Set 1 to the
bit will clear it.
0: No effect, 1: Pending.
28
R/W
0x0
DDMA6_HF_IRQ_PEND
Dedicated DMA 6 Half Transfer Interrupt Pending. Set 1 to the
bit will clear it.
0: No effect, 1: Pending.
27
R/W
0x0
DDMA5_END_IRQ_PEND
Dedicated DMA 5 End Transfer Interrupt Pending. Set 1 to the
bit will clear it.
0: No effect, 1: Pending.
26
R/W
0x0
DDMA5_HF_IRQ_PEND
Dedicated DMA 5 Half Transfer Interrupt Pending. Set 1 to the
bit will clear it.
0: No effect, 1: Pending.
25
R/W
0x0
DDMA4_END_IRQ_PEND
Dedicated DMA 4 End Transfer Interrupt Pending. Set 1 to the
bit will clear it.
0: No effect, 1: Pending.
24
R/W
0x0
DDMA4_HF_IRQ_PEND
Dedicated DMA 4 Half Transfer Interrupt Pending. Set 1 to the
bit will clear it.
0: No effect, 1: Pending.
23
R/W
0x0
DDMA3_END_IRQ_PEND