Allwinner A20 - Page 158

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 158 / 812
Offset: 0x4
Register Name: DMA_IRQ_PEND_STA_REG
Bit
Read/
Write
Default/Hex
Description
Dedicated DMA 3 End Transfer Interrupt Pending. Set 1 to the
bit will clear it.
0: No effect, 1: Pending.
22
R/W
0x0
DDMA3_HF_IRQ_PEND
Dedicated DMA 3 Half Transfer Interrupt Pending. Set 1 to the
bit will clear it.
0: No effect, 1: Pending.
21
R/W
0x0
DDMA2_END_IRQ_PEND
Dedicated DMA 2 End Transfer Interrupt Pending. Set 1 to the
bit will clear it.
0: No effect, 1: Pending.
20
R/W
0x0
DDMA2_HF_IRQ_PEND
Dedicated DMA 2 Half Transfer Interrupt Pending. Set 1 to the
bit will clear it.
0: No effect, 1: Pending.
19
R/W
0x0
DDMA1_END_IRQ_PEND
Dedicated DMA 1 End Transfer Interrupt Pending. Set 1 to the
bit will clear it.
0: No effect, 1: Pending.
18
R/W
0x0
DDMA1_HF_IRQ_PEND
Dedicated DMA 1 Half Transfer Interrupt Pending. Set 1 to the
bit will clear it.
0: No effect, 1: Pending.
17
R/W
0x0
DDMA0_END_IRQ_PEND
Dedicated DMA 0 End Transfer Interrupt Pending. Set 1 to the
bit will clear it.
0: No effect, 1: Pending.
16
R/W
0x0
DDMA0_HF_IRQ_PEND
Dedicated DMA 0 Half Transfer Interrupt Pending. Set 1 to the
bit will clear it.
0: No effect, 1: Pending.
15
R/W
0x0
NDMA7_END_IRQ_PEND.
Normal DMA 7 End Transfer Interrupt Pending. Set 1 to the bit
will clear it.
0: No effect, 1: Pending.
14
R/W
0x0
NDMA7_HF_IRQ_PEND.
Normal DMA 7 Half Transfer Interrupt Pending. Set 1 to the bit