Allwinner A20 - Page 159

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 159 / 812
Offset: 0x4
Register Name: DMA_IRQ_PEND_STA_REG
Bit
Read/
Write
Default/Hex
Description
will clear it.
0: No effect, 1: Pending.
13
R/W
0x0
NDMA6_END_IRQ_PEND.
Normal DMA 6 End Transfer Interrupt Pending. Set 1 to the bit
will clear it.
0: No effect, 1: Pending.
12
R/W
0x0
NDMA6_HF_IRQ_PEND.
Normal DMA 6 Half Transfer Interrupt Pending. Set 1 to the bit
will clear it.
0: No effect, 1: Pending.
11
R/W
0x0
NDMA5_END_IRQ_PEND.
Normal DMA 5 End Transfer Interrupt Pending. Set 1 to the bit
will clear it.
0: No effect, 1: Pending.
10
R/W
0x0
NDMA5_HF_IRQ_PEND.
Normal DMA 5 Half Transfer Interrupt Pending. Set 1 to the bit
will clear it.
0: No effect, 1: Pending.
9
R/W
0x0
NDMA4_END_IRQ_PEND.
Normal DMA 4 End Transfer Interrupt Pending. Set 1 to the bit
will clear it.
0: No effect, 1: Pending.
8
R/W
0x0
NDMA4_HF_IRQ_PEND.
Normal DMA 4 Half Transfer Interrupt Pending. Set 1 to the bit
will clear it.
0: No effect, 1: Pending.
7
R/W
0x0
NDMA3_END_IRQ_PEND.
Normal DMA 3 End Transfer Interrupt Pending. Set 1 to the bit
will clear it.
0: No effect, 1: Pending.
6
R/W
0x0
NDMA3_HF_IRQ_PEND.
Normal DMA 3 Half Transfer Interrupt Pending. Set 1 to the bit
will clear it.
0: No effect, 1: Pending.
5
R/W
0x0
NDMA2_END_IRQ_PEND.
Normal DMA 2 End Transfer Interrupt Pending. Set 1 to the bit