Allwinner A20 - PS2 Register List; PS2 Register Description

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 633 / 812
Name
Comment
Min.
Typical
Max.
Trsp
Time for device responding to the host command
-
-
20ms
6.5.4. PS2 Register List
Module Name
Base Address
PS2-0
0x01C2A000
PS2-1
0x01C2A400
Register Name
Offset
Description
PS2_GCTL
0x00
PS2 Module Global Control Register
PS2_DATA
0x04
PS2 Module Data Register
PS2_LCTL
0x08
PS2 Module Line Control Register
PS2_LSTS
0x0C
PS2 Module Line Status Register
PS2_FCTL
0x10
PS2 Module FIFO Control Register
PS2_FSTS
0x14
PS2 Module FIFO Status Register
PS2_CKDR
0x18
PS2 Module Clock Divider Register
6.5.5. PS2 Register Description
6.5.5.1. PS2 GLOBAL CONTROL REGISTER
Offset: 0x0000
Register Name: PS2_GCTL
Default Value: 0x0000_0002
Bit
Read/Write
Default
Description
31:5
/
/
/
4
R
0
INT_FLAG
Interrupt Flag
The interrupt flag is set when any bit in FIFO Status and the
corresponding enable bit in FIFO Control are set at the same
time. This interrupt flag is also set when error flag bit in line
status register
(
PS2_LSTS
)
is set at the same time.