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Allwinner A20 - Page 632

Allwinner A20
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A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 632 / 812
Timing for Master Transmit Data and Device Receive Data:
STA
D0
D1
D2
D3
D4
D5
D6
D7
PAR
STP
ACK
STA
D0
D1
D2
D3
D4
D5
D6
D7
PAR
STP
ACK
TdataTdataTc2c
Tf2dTd2r
TckhTckhTcklTcklTinhTinh
CLOCK
DATA
HOST_CLOCK
HOST_DATA
DEVICE_CLOCK
DEVICE_DATA
Timing for Master sending command then Device sending response
STA
D0
D1
D7
PAR
STP
ACK
STA
D0
D1
D7
PAR
STP
TrspTrsp
device responds to host
Host sends command to device
CLOCK
DATA
Device drive and sample data at rising edge of CLOCK. Master drive and sample data at falling edge
of CLOCK.
Name
Comment
Min.
Typical
Max.
Tckl
Clock LOW time
30us
40us
50us
Tckh
Clock HIGH time
30us
40us
50us
Tinh
Time for Host inhibit clock for send data request
100us
-
-
Td2f
Data change to clock falling edge time during device to
host transfer
5us
-
Tckh-5us
Tr2d
Clock rising edge to data change time during device to
host transfer
5us
-
Tckh-5us
Td2r
Data change to clock rising edge time during host to
device transfer
5us
-
Tckl-5us
Tf2d
Clock falling edge to data change time during host to
device transfer
5us
-
Tckl-5us
Tc2c
Host pull low Clock to Device drive Clock
-
-
15ms
Tdata
Time for packet to send
-
-
2ms

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