Allwinner A20 - Timer Register Description

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 110 / 812
Register Name
Offset
Description
RTC_YY_MM_DD_REG
0x104
RTC Year-Month-Day Register
RTC_HH_MM_SS_REG
0x108
RTC Hour-Minute-Second Register
DD_HH_MM_SS_REG
0x10C
Alarm Day-Hour-Minute-Second Register
ALARM_WK_HH_MM-SS
0x110
Alarm Week HMS Register
ALARM_EN_REG
0x114
Alarm Enable Register
ALARM_IRQ_EN
0x118
Alarm IRQ Enable Register
ALARM_IRQ_STA_REG
0x11C
Alarm IRQ Status Register
TMR_GP_DATA_REG
0x120 + N*0x4
Timer General Purpose Register
(N=0~15)
ALARM_CONFIG_REG
0x170
Alarm Config Register
1.9.3. Timer Register Description
1.9.3.1. TIMER IRQ ENABLE REGISTER(DEFAULT: 0X00000000)
Offset: 0x0
Register Name: TMR_IRQ_EN_REG
Bit
Read/
Write
Default/Hex
Description
31:9
/
/
/.
8
R/W
0x0
WDOG_IRQ_EN.
Watchdog Interrupt Enable.
0: No effect, 1: watchdog Interval Value reached interrupt
enable.
7:6
/
/
/
5
R/W
0x0
TMR5_IRQ_EN.
Timer 5 Interrupt Enable.
0: No effect, 1: Timer 5 Interval Value reached interrupt enable.
4
R/W
0x0
TMR4_IRQ_EN.
Timer 4 Interrupt Enable.
0: No effect, 1: Timer 4 Interval Value reached interrupt enable.
3
R/W
0x0
TMR3_IRQ_EN.
Timer 3 Interrupt Enable.