Allwinner A20 - Page 111

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 111 / 812
Offset: 0x0
Register Name: TMR_IRQ_EN_REG
Bit
Read/
Write
Default/Hex
Description
0: No effect, 1: Timer 3 Interval Value reached interrupt enable.
2
R/W
0x0
TMR2_IRQ_EN.
Timer 2 Interrupt Enable.
0: No effect, 1: Timer 2 Interval Value reached interrupt enable.
1
R/W
0x0
TMR1_IRQ_EN.
Timer 1 Interrupt Enable.
0: No effect, 1: Timer 1 Interval Value reached interrupt enable.
0
R/W
0x0
TMR0_IRQ_EN.
Timer 0 Interrupt Enable.
0: No effect, 1: Timer 0 Interval Value reached interrupt enable.
1.9.3.2. TIMER IRQ STATUS REGISTER(DEFAULT: 0X00000000)
Offset: 0x4
Register Name: TMR_IRQ_STA_REG
Bit
Read/
Write
Default/Hex
Description
31:9
/
/
/.
8
R/W
0x0
WDOG_IRQ_PEND.
Watchdog IRQ Pending. Set 1 to the bit will clear it.
0: No effect, 1: Pending, Watchdog counter value is reached.
7:6
/
/
/
5
R/W
0x0
TMR5_IRQ_PEND.
Timer 5 IRQ Pending. Set 1 to the bit will clear it.
0: No effect, 1: Pending, timer 5 counter value is reached.
4
R/W
0x0
TMR4_IRQ_PEND.
Timer 4 IRQ Pending. Set 1 to the bit will clear it.
0: No effect, 1: Pending, timer 4 counter value is reached.
3
R/W
0x0
TMR3_IRQ_PEND.
Timer 3 IRQ Pending. Set 1 to the bit will clear it.
0: No effect, 1: Pending, timer 3 counter value is reached.
2
R/W
0x0
TMR2_IRQ_PEND.
Timer 2 IRQ Pending. Set 1 to the bit will clear it.
0: No effect, 1: Pending, timer 2 counter value is reached.