Allwinner A20 - Digital Audio Interface Block Diagram; Digital Audio Interface Timing Diagram

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 698 / 812
6.9.2. Digital Audio Interface Block Diagram
The Digital Audio Interface block diagram is shown below:
Register
128x24-
bits
RX FIFO
I2S
Engine
PCM
Engine
PCM
Codec
Clock
Divide
M
U
X
S
Y
N
C
MCLK
BCLK
I2S_SCLK/PCM_CLK
I2S_LRC/PCM_SYNC
I2S_SDO/PCM_OUT(4)
I2S_SDI/PCM_IN
TX_DRQ RX_DRQ
Audio_PLL
DA_INT
APB
64x24-bits
TX FIFO
6.9.3. Digital Audio Interface Timing Diagram
Left Channel
Right Channel
MSB
LSB
MSB
LSB
Standard I2S Timing Diagram
I2S_LRC
I2S_SCLK
I2S_SDO/SDI