Allwinner A20 - High Speed Timer Controller Register

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 136 / 812
1.10.3. High Speed Timer Controller Register
1.10.3.1. HS TIMER IRQ ENABLE REGISTER (DEFAULT: 0X00000000)
Offset:0x0
Register Name: HS_TMR_IRQ_EN_REG
Bit
Read/
Write
Default/He
x
Description
31:4
/
/
/
3
R/W
0x0
HS_TMR3_INT_EN.
High Speed Timer 3 Interrupt Enable.
0: No effect;
1: High Speed Timer 3 Interval Value reached interrupt
enable.
2
R/W
0x0
HS_TMR2_INT_EN.
High Speed Timer 2 Interrupt Enable.
0: No effect;
1: High Speed Timer 2 Interval Value reached interrupt
enable.
1
R/W
0x0
HS_TMR1_INT_EN.
High Speed Timer 1 Interrupt Enable.
0: No effect;
1: High Speed Timer 1 Interval Value reached interrupt
enable.
0
R/W
0x0
HS_TMR0_INT_EN.
High Speed Timer 0 Interrupt Enable.
0: No effect;
1: High Speed Timer 0 Interval Value reached interrupt
enable.
1.10.3.2. HS TIMER IRQ STATUS REGISTER (DEFAULT: 0X00000000)
Offset:0x4
Register Name: HS_TMR_IRQ_STAS_REG
Bit
Read/
Write
Default/Hex
Description
31:4
/
/
/
3
R/W
0x0
HS_TMR3_IRQ_PEND.
High Speed Timer 3 IRQ Pending. Set 1 to the bit will clear it.
0: No effect;