Allwinner A20 - Page 137

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 137 / 812
Offset:0x4
Register Name: HS_TMR_IRQ_STAS_REG
Bit
Read/
Write
Default/Hex
Description
1: Pending, High speed timer 3 interval value is reached.
2
R/W
0x0
HS_TMR2_IRQ_PEND.
High Speed Timer 2 IRQ Pending. Set 1 to the bit will clear it.
0: No effect;
1: Pending, High speed timer 2 interval value is reached.
1
R/W
0x0
HS_TMR1_IRQ_PEND.
High Speed Timer 1 IRQ Pending. Set 1 to the bit will clear it.
0: No effect;
1: Pending, High speed timer 1 interval value is reached.
0
R/W
0x0
HS_TMR0_IRQ_PEND.
High Speed Timer 0 IRQ Pending. Set 1 to the bit will clear it.
0: No effect;
1: Pending, High speed timer 0 interval value is reached.
1.10.3.3. HS TIMER 0 CONTROL REGISTER (DEFAULT: 0X00000000)
Offset:0x10
Register Name: HS_TMR0_CTRL_REG
Bit
Read/
Write
Default/He
x
Description
31
R/W
0x0
/
30:8
/
/
/
7
R/W
0x0
HS_TMR0_MODE.
High Speed Timer 0 mode.
0: Continuous mode. When interval value reached, the timer
will not disable automatically.
1: Single mode. When interval value reached, the timer will
disable automatically.
6:4
R/W
0x0
HS_TMR0_CLK
Select the pre-scale of the high speed timer 0 clock sources.
000: /1
001: /2
010: /4
011: /8
100: /16