Allwinner A20 - 1.7. System Control

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 97 / 812
1.7. System Control
1.7.1. Overview
The chip embeds a high-speed SRAM. This internal SRAM is split into five areas, and its memory
mapping can be seen below:
Area
Address
Size(Bytes)
A1
0x00000000--0x00003FFF
16K
A2
0x00004000--0x00007FFF
16K
A3
0x00008000--0x0000B3FF
13K
A4
0x0000B400--0x0000BFFF
3K
C1
0x01D00000-0x01D7FFFF
VE
NAND
2K
D( USB )
0x00010000—0x00010FFF
4K
B(Secure RAM)
0x00020000--0x0002FFFF
64K
CPU0 I-Cache
32K
CPU0 D-Cache
32K
CPU1 I-Cache
32K
CPU1 D-Cache
32K
CPU L2 Cache
256K
Total
502K