Allwinner A20 - Port Register Description

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 239 / 812
Register Name
Offset
Description
Pn_DRV0
n*0x24+0x14
Port n Multi-Driving Register 0 (n from 0 to 8)
Pn_DRV1
n*0x24+0x18
Port n Multi-Driving Register 1 (n from 0 to 8)
Pn_PUL0
n*0x24+0x1C
Port n Pull Register 0 (n from 0 to 8)
Pn_PUL1
n*0x24+0x20
Port n Pull Register 1 (n from 0 to 8)
PIO_INT_CFG0
0x200
PIO Interrrupt Configure Register 0
PIO_INT_CFG1
0x204
PIO Interrrupt Configure Register 1
PIO_INT_CFG2
0x208
PIO Interrrupt Configure Register 2
PIO_INT_CFG3
0x20C
PIO Interrrupt Configure Register 3
PIO_INT_CTL
0x210
PIO Interrupt Control Register
PIO_INT_STA
0x214
PIO Interrupt Status Register
PIO_INT_DEB
0x218
PIO Interrupt Debounce Register
1.19.4. Port Register Description
1.19.4.1. PA CONFIGURE REGISTER 0
Offset: 0x00
Register Name: PA_CFG0
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31
/
/
/
30:28
R/W
0
PA7_SELECT
000: Input 001: Output
010:ETXD0 011: SPI3_MOSI
100: Reserved 101: GTXD0
110: Reserved 111: Reserved
27
/
/
Reserved
26:24
R/W
0
PA6_SELECT
000: Input 001: Output
010: ETXD1 011: SPI3_CLK
100: Reserved 101: GTXD1
110: Reserved 111: Reserved