Allwinner A20 - 1.5. CCU

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 34 / 812
1.5. CCU
1.5.1. Overview
The CCU (Clock Control Unit) is made up of 8 PLLs, a main oscillator, an on-chip RC oscillator and a
32768Hz low-power oscillator.
A20 integrates two crystal oscillators: The 24MHz crystal is mandatory, which is used to provide clock
source for the PLL and the main digital blocks, and the 32768Hz oscillator, which is only used to
provide a low power, accurate reference for the RTC.
A20 also provides following clock domain to allow for user interfaces of high performance and low
power consumption.
Clock Domain
Module
Speed Range
Description
OSC24M
Most Clock Generator
24MHz
Root clock for most blocks
RC_osc
Timer,Key
32KHz
Source for the RTC/Timer
32K768Hz
Timer,Key
32768Hz
Low-power source for the RTC/Timer
CPU32_clk
CPU32
2K~1200M
Divided from CPU32_clk or OSC24M
AHB_clk
AHB Devices
8K~276M
Divided from CPU32_clk
APB_clk
Peripheral
0.5K~138M
Divided from AHB_clk
SDRAM_clk
SDRAM
0~400MHz
Sourced from the PLL
USB_clk
USB
480MHz
Sourced from the PLL
Audio_clk
A/D,D/A
24.576MHz
/22.5792MHz
Sourced from the PLL
The CCU features:
 8 PLLs, a main oscillator, an on-chip RC oscillator and a 32768Hz low-power oscillator
 PLL1 is the main clock of CPU0/1
 Clock configuration for corresponding module
 Software-controlled clock gating
 2 clock output channels