Allwinner A20 - Display Engine Block Diagram; DEBE Register List

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 529 / 812
5.4.2. Display Engine Block Diagram
PIPE 1 FIFO
PIPE 0 FIFO
On Chip
Frame
SRAM
Normal/YUV/Palette/Gamma/Internal
frame buffer Controller
Alpha
Blender 1
Alpha
Blender 0
H W Cursor
pattern buffer
Intelligent
Ext DMA
Controller
DE Front-End DE Back-End
LCD Controller
TV Encoder
Alpha
Blender 2
Sprite controller
Write back channel
Color &
Keystone
Correction
AHB BUS
Dedicated DRAM Access BUS
FE0
FE1
5.4.3. DEBE Register list
Module name
Base Address
BE0
0x01e60000
BE1
0x01e40000
Register name
Offset
Description
DEBE_MODCTL_REG
0x800
DE back-end mode control register
DEBE_BACKCOLOR_REG
0x804
DE-back color control register
DEBE_DISSIZE_REG
0x808
DE-back display size setting register
DEBE_LAYSIZE_REG
0x810 – 0x81C
DE-layer size register
DEBE_LAYCOOR_REG
0x820 – 0x82C
DE-layer coordinate control register
DEBE_LAYLINEWIDTH_REG
0x840 – 0x84C
DE-layer frame buffer line width register
DEBE_LAYFB_L32ADD_REG
0x850 – 0x85C
DE-layer frame buffer low 32 bit address
register